An overhead view of a traffic interchange at night.

Capital capabilities

Network design software

Networks are a critical aspect of all modern vehicles. Use Capital to help design ‘right-sized’ communications networks with detailed timing analysis, optimize and verify network designs to ensure quality and accelerate development, and deliver accurate communication network implementation.

Safety-critical timing

Leverage advanced methods to tackle the new dimension of complex real-time systems using distributed communication with correct timing.

Network design time cut by 50%

Automate, accelerate and simplify systems design to save time and focus on high-value tasks that help you differentiate and win in the marketplace.

Rapid design of validated and correct networks

Optimize communication for the entire distributed communication system – maximize usage of each communication cluster (bus).

Accelerate design of networks with guaranteed delivery

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SLEC System Factsheet
Fact Sheet

SLEC System Factsheet

SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models

Catapult High-Level Synthesis and Verification Fact Sheet
Fact Sheet

Catapult High-Level Synthesis and Verification Fact Sheet

Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL.

StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses
White Paper

StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses

StreamTV's SeeCubic faced an impossible task: develop a real-time conversion IP block for a custom SoC without knowing the target technology. This IP was critical for their glasses-free 3D solution.